MSI PM-104 Series Spécifications

XIO3130XIO3130Data ManualPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasIn

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4-79 Bit Descriptions – Link Status Register ...

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.3.30 Capability ID RegisterThis read-only register identifies the linked list item as the re

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-67. Bit Descriptions – Power Management Capabilities Register (continued)BIT FIELD NAME

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.3.34 Power Management Bridge Support Extension RegisterThis read-only register is used to in

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010BIT NUMBER 7 6 5 4 3 2 1 0RESET STATE 1 0 0 0 0 0 0 04.3.38 MSI Message Control RegisterThis re

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-71. Bit Descriptions – MSI Message Address RegisterBIT FIELD NAME ACCESS DESCRIPTION31

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010BIT NUMBER 7 6 5 4 3 2 1 0RESET STATE 0 0 0 0 1 1 0 1Copyright © 2007–2010, Texas Instruments I

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.3.43 Next-Item Pointer RegisterThe contents of this read-only register indicate the next ite

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.3.47 Next-Item Pointer RegisterThe contents of this read-only register indicate the next item

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-74. Bit Descriptions – Device Capabilities RegisterBIT FIELD NAME ACCESS DESCRIPTION31

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-75. Bit Descriptions – Device Control Register (continued)BIT FIELD NAME ACCESS DESCRIP

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010XIO3130Check for Samples: XIO31301 Features12• PCI Express Base Specification, Revision 1.1 • S

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-76. Bit Descriptions – Device Status RegisterBIT FIELD NAME ACCESS DESCRIPTION15:6 RSV

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-77. Bit Descriptions – Link Capabilities Register (continued)BIT FIELD NAME ACCESS DESC

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-78. Bit Descriptions – Link Control Register (continued)BIT FIELD NAME ACCESS DESCRIPT

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RESET STATE 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0Tabl

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-80. Bit Descriptions – Slot Capabilities Register (continued)BIT FIELD NAME ACCESS DES

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-81. Bit Descriptions – Slot Control Register (continued)BIT FIELD NAME ACCESS DESCRIPTI

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-81. Bit Descriptions – Slot Control Register (continued)BIT FIELD NAME ACCESS DESCRIPT

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-82. Bit Descriptions – Slot Status Register (continued)BIT FIELD NAME ACCESS DESCRIPTIO

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.3.60 TI Proprietary RegisterThis read/write TI proprietary register is located at offset D0h

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-83. Bit Descriptions – General Control Register (continued)BIT FIELD NAME ACCESS DESCRI

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com2 IntroductionThe Texas Instruments XIO3130 switch is an integrated PCI Express fanout switch

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-83. Bit Descriptions – General Control Register (continued)BIT FIELD NAME ACCESS DESCR

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Tabl

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-85. Uncorrectable Error Status RegisterBIT FIELD NAME ACCESS DESCRIPTION31:21 RSVD r R

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-86. Uncorrectable Error Mask Register (continued)BIT FIELD NAME ACCESS DESCRIPTIONMalfo

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-87. Uncorrectable Error Severity RegisterBIT FIELD NAME ACCESS DESCRIPTION31:21 RSVD r

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-89. Correctable Error Mask Register (continued)BIT FIELD NAME ACCESS DESCRIPTIONBad DL

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Register type: Read onlyDefault value: 0000 0000hBIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com5 PCI Hot Plug Implementation Overview5.1 PCI Hot Plug Architecture OverviewThe PCI Express ar

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 5-1. GPIO Matrix (continued)GPIO[#] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16EMILENG3 7 7I

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20102.3 Document ConventionsThroughout this data manual, several conventions are used to convey inf

PERSTn#REFCLKnPERST#StableUnstable<100 smPWRGDnCLKREQn#REFCLKnPERSTn#PWRONn#Unstable Stable100ms>100 smXIO3130SLLS693F–MAY 2007 –REVISED JANUAR

PWRGDnCLKREQn#REFCLKnPERSTn#PWRONn#Unstable Stable100ms>100 sm100msPWRGDnCLKREQn#REFCLKnPERSTn#PWRONn#Stable<100 smXIO3130www.ti.comSLLS693F–

PWRONn#CLKREQn#REFCLKnPERSTn#PRSNTn#StablePWRGDn<500ns<100 smPWRONn#CLKREQn#REFCLKnPERSTn#PWRGDnStable Unstable Stable<500ns100ms>100 s

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20105.2.4 Debounce CircuitsIntegrated de-bounce circuits are provided for the following input pins:

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com6 Electrical CharacteristicsThis chapter describes the electrical characteristics of the XIO31

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20106.3 PCI Express Differential Transmitter Output RangesPARAMETER TERMINALS MIN NOM MAX UNIT COMM

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comPCI Express Differential Transmitter Output Ranges (continued)PARAMETER TERMINALS MIN NOM MAX

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010PCI Express Differential Receiver Input Ranges (continued)PARAMETER TERMINALS MIN NOM MAX UNIT

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com6.6 PCI Express Reference Clock Output Requirements100-MHz INPUTSYMBOL PARAMETER UNIT NOTESMIN

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20106.7 3.3-V I/O Electrical Characteristics(1)PARAMETER OPERATIONS TEST CONDITIONS MIN MAX UNITVIH

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com2.5 Terminal AssignmentsThe XIO3130 is packaged in a 196-ball ZHC MicroStar™ BGA.Table 2-1. XI

PACKAGE OPTION ADDENDUMwww.ti.com15-Dec-2014Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEc

PACKAGE OPTION ADDENDUMwww.ti.com15-Dec-2014Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total pur

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 2-2. XIO3130 Terminals Sorted AlphanumericallyBall Signal Name Ball Signal Name Ball Sign

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 2-3. XIO3130 Signal Names Sorted AlphabeticallySignal Name Ball Signal Name BallCLKREQ_U

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20102.6 Terminal DescriptionsTable 2-4. Power Supply TerminalsSignal Ball I/O Type External parts D

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 2-6. Ground TerminalsSignal Ball I/O Type DescriptionD05, D06, D10, D11, E05,E06, E07, E

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 2-8. PCI Express TerminalsSignal Ball I/O Type External Parts DescriptionUP_PETp G01 HS D

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comContents1 Features ...

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 2-10. GPIO TerminalsSignal Ball I/O Type External Parts DescriptionGPIO 0. If the DN1_DP

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 2-11. Miscellaneous TerminalsSignal Ball I/O Type External Parts DescriptionC02 LV CMOS I

PCIExpressX1 PhyPort0(Up)LogicVirtualPCItoPCIBridgePort1(Down)LogicPort2(Down)LogicPort3(down)logicGPIOPCI HotPlugEEPROMClockDistribution/ResetL

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Figure 3-2. Power-Up Sequence Diagram3.1.2 Power-Down Sequence• Assert PERST to the device.• Re

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com3.2.3 BeaconThe XIO3130 supports the PCI Express in-band beacon feature. Beacon is driven on t

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 3-2. Messages Supported by the XIO3130Message Supported XIO3130 ActionAssert_INTx Yes Pas

XIO3130SCLSDASERIALEEPROMSCL A2A1SDA A0VDD3 3XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comedge of PERST or GRST, whichever occurs last, the

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Figure 3-5. Serial-Bus Start/Stop Conditions and Bit TransfersData is transferred serially in 8

Sb6 b1b2b3b4b5 b0 1 Ab7 b6 b1b2b3b4b5 b0 ASlave AddressWord AddressStartR/WSRestartb6 b1b2b3b4b5 b0 0 ASlave AddressR/Wb7 b6 b1b2b3b4b5 b0 MDataByteP

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010• EEPROM bytes 28h through 35h correspond to and are loaded into the configuration space for th

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.2.17 Secondary Status Register ...

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 3-3. EEPROM Register Loading Map (continued)EEPROM Byte Address Suggested Programmed CON

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010This download table must be explicitly followed for the XIO3130 to correctly load initializatio

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 3-5. Switch Reset OptionsReset Option XIO3130 Feature Reset ResponseInternally-generated

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104 XIO3130 Configuration Register SpaceThis chapter specifies the configuration registers that a

**Examplevalues.Actualbusnumbers may change based on system hierarchy.Virtual Internal PCI BusDownstream PortHeader Type 01hPCI CapabilityStructu

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.2.1 PCI Configuration Space (Upstream Port) Register MapTable 4-1. PCI Express Upstream Port

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-2. Extended Configuration Space (Upstream Port)Register Name OffsetNext Capability Off

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-3. Bit Descriptions – Command RegisterBIT FIELD NAME ACCESS DESCRIPTION15:11 RSVD r Res

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-4. Bit Descriptions – Status RegisterBIT FIELD NAME ACCESS DESCRIPTIONDetected parity

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.2.6 Class Code and Revision ID RegisterThis read-only register categorizes the Base Class, Su

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.62 GPIO B Control Register ...

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.9 Header Type RegisterThis read-only register indicates that this function has a type one

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.2.13 Subordinate Bus NumberThis register specifies the bus number of the highest number PCI b

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.16 I/O Limit RegisterThis read/write register specifies the upper limit of the I/O address

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.2.18 Memory Base RegisterThis read/write register specifies the lower limit of the memory add

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-11. Bit Descriptions – Pre-fetchable Memory Base RegisterBIT FIELD NAME ACCESS DESCRIP

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.2.23 Pre-fetchable Limit Upper 32 Bits RegisterThis read/write register specifies the upper 3

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.26 Capabilities Pointer RegisterThis read-only register provides a pointer into the PCI co

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-17. Bit Descriptions – Bridge Control RegisterBIT FIELD NAME ACCESS DESCRIPTION15:12 RS

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-17. Bit Descriptions – Bridge Control Register (continued)BIT FIELD NAME ACCESS DESCRI

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-18. Bit Descriptions – Power Management Capabilities Register (continued)BIT FIELD NAME

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.3.22 Pre-fetchable Base Upper 32 Bits Register ...

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.34 Power Management Bridge Support Extension RegisterThis read-only register is used to in

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010BIT NUMBER 7 6 5 4 3 2 1 0RESET STATE 1 0 0 0 0 0 0 04.2.38 MSI Message Control RegisterThis re

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-22. Bit Descriptions – MSI Message Address RegisterBIT FIELD NAME ACCESS DESCRIPTION31

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010BIT NUMBER 7 6 5 4 3 2 1 0RESET STATE 0 0 0 0 1 1 0 14.2.43 Next-Item Pointer RegisterThe conte

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.47 Next-Item Pointer RegisterThe contents of this read-only register indicate the next ite

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-25. Bit Descriptions – Device Capabilities RegisterBIT FIELD NAME ACCESS DESCRIPTION31:

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-26. Bit Descriptions – Device Control Register (continued)BIT FIELD NAME ACCESS DESCRI

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-27. Bit Descriptions – Device Status RegisterBIT FIELD NAME ACCESS DESCRIPTION15:6 RSVD

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-28. Bit Descriptions – Link Capabilities Register (continued)BIT FIELD NAME ACCESS DES

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.2.54 Link Status RegisterThe Link Status register indicates the current state of the PCI Expr

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.3.67 Uncorrectable Error Mask Register ...

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.57 Serial Bus Slave Address RegisterThe Serial Bus Slave Address register is used to indic

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-32. Bit Descriptions – Serial Bus Control and Status Register (continued)BIT FIELD NAME

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-33. Bit Descriptions – Upstream Port Link PM Latency RegisterBIT FIELD NAME ACCESS DES

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-33. Bit Descriptions – Upstream Port Link PM Latency Register (continued)BIT FIELD NAME

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-34. Bit Descriptions – Global Chip Control Register (continued)BIT FIELD NAME ACCESS D

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Tabl

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-35. Bit Descriptions – GPIO A Control Register (continued)BIT FIELD NAME ACCESS DESCRI

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-36. Bit Descriptions – GPIO B Control RegisterBIT FIELD NAME ACCESS DESCRIPTION15 RSVD

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-36. Bit Descriptions – GPIO B Control Register (continued)BIT FIELD NAME ACCESS DESCRI

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-37. Bit Descriptions – GPIO C Control RegisterBIT FIELD NAME ACCESS DESCRIPTION15 RSVD

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010List of Figures3-1 Block Diagram ...

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-37. Bit Descriptions – GPIO C Control Register (continued)BIT FIELD NAME ACCESS DESCRI

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-38. Bit Descriptions – GPIO D Control RegisterBIT FIELD NAME ACCESS DESCRIPTION15:10 RS

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.65 GPIO Data RegisterThis register is used to read the state of the GPIO pins and to chang

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-39. Bit Descriptions – GPIO Data Register (continued)BIT FIELD NAME ACCESS DESCRIPTIONG

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-39. Bit Descriptions – GPIO Data Register (continued)BIT FIELD NAME ACCESS DESCRIPTION

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.2.66 TI Proprietary RegisterThis read/write TI proprietary register is located at offset C8h

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.69 TI Proprietary RegisterThis read/write TI proprietary register is located at offset D4h

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.2.72 Subsystem Access RegisterThis register is a read/write register. The contents of this re

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.74 Downstream Ports Link PM Latency RegisterThis read/write register is used to program L0

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-42. Bit Descriptions – Downstream Ports Link PM Latency Register (continued)BIT FIELD N

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comList of Tables2-1 XIO3130 Terminal Assignments...

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-43. Bit Descriptions – Global Switch Control Register (continued)BIT FIELD NAME ACCESS

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-44. Uncorrectable Error Status RegisterBIT FIELD NAME ACCESS DESCRIPTION31:21 RSVD r Re

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-45. Uncorrectable Error Mask Register (continued)BIT FIELD NAME ACCESS DESCRIPTIONMalf

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-46. Uncorrectable Error Severity RegisterBIT FIELD NAME ACCESS DESCRIPTION31:21 RSVD r

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comBIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-48. Correctable Error Mask Register (continued)BIT FIELD NAME ACCESS DESCRIPTIONREPLAY_

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.2.84 Header Log RegisterThe Header Log register stores the TLP header for the packet that le

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.3 PCI Express Downstream Port RegistersThe default reset domain for all downstream port regis

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-51. Extended Configuration Space (Downstream Port)Register Name OffsetNext Capability

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-52. Bit Descriptions – Command RegisterBIT FIELD NAME ACCESS DESCRIPTION15:11 RSVD r Re

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104-31 Bit Descriptions – Serial Bus Slave Address Register ...

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-53. Bit Descriptions – Status Register (continued)BIT FIELD NAME ACCESS DESCRIPTIONRec

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.3.7 Cache Line Size RegisterThe Cache Line Size register is implemented by PCI Express device

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.3.11 Primary Bus NumberThis register specifies the bus number of the PCI bus segment for the

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.3.15 I/O Base RegisterThis read/write register specifies the lower limit of the I/O addresses

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-57. Bit Descriptions – Secondary Status RegisterBIT FIELD NAME ACCESS DESCRIPTIONDetec

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.3.19 Memory Limit RegisterThis read/write register specifies the upper limit of the memory ad

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.comTable 4-61. Bit Descriptions – Pre-fetchable Memory Limit RegisterBIT FIELD NAME ACCESS DESCRI

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 20104.3.24 I/O Base Upper 16 Bits RegisterThis read/write register specifies the upper 16 bits of t

XIO3130SLLS693F–MAY 2007 –REVISED JANUARY 2010www.ti.com4.3.27 Interrupt Line RegisterThis read/write register, which the system programs, indicates t

XIO3130www.ti.comSLLS693F–MAY 2007–REVISED JANUARY 2010Table 4-66. Bit Descriptions – Bridge Control Register (continued)BIT FIELD NAME ACCESS DESCRIP